ABSTRACT: Adders are the main component in digital devices. In this work circuit for XOR/XNOR gates are used. The design of full adder using XOR/XNOR gates is used. This circuit design is highly optimized in terms of power and delay. This circuit is designed by using 65nm technology. So we designed a new circuit by using GDI technique. The design of full adder using GDI technique also reduces the transistor sizing, thereby it also reduces the power and speed.it is designed by using 18nm technology. Our observation shows the comparison of both techniques in tanner platform.
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Many existing XOR-XNOR cells suffer from non-full-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR XNOR cell, is presented. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive TSPICE and TANNER simulations are for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. The full swing XOR/XNOR and non-full swing XOR/XNOR gate circuits are used to propose new Full Adder design in order to optimize power, delay and PDP (Power delay product) of the low power circuits. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs performed.
Abstract: XOR and XNOR gates play an important role in digital systems. XOR & XNOR logic gates are basic building blocks of many arithmetic circuits. The XOR and XNOR circuit is implemented in pass transistor logic, static CMOS logic, transmission gate logic. The design of the XOR & XNOR circuits based on TSMC 32nm process models at the supply voltage 0.9V is simulated using HSPICE. Due to low power consumption and high speed these design circuits are suitable for arithmetic operations and VLSI applications. Hence comparison of delay & power is obtained in this paper for various design techniques of logic gates.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Complementary pass transistor logic (CPL) is used in . Wang et al.  report the XOR-XNOR circuits based on transmission gates. It uses eight transistors and complementary inputs and has a drawback of loss of driving capability. Wang et al. also designed XOR-XNOR circuits based on inverter gates. It does not require a complementary inputs but it has no driving capability because there is no direct connection to Vdd and Gnd. The improved version of this circuit has been designed by adding a standard inverter to the output. This modified circuit provides a good driving capability but uses twelve transistors for XOR-XNOR circuits.
Abstract-- Full adder is the basic digital components for the region many improvements have been made to improve its architecture. In this paper, we present GDI (Gate-Diffusion Input) structure and hybrid logic style with 12 transistors without losing the characteristic of the circuits. The main design objectives for these adder cell modules are providing Low-Power dissipation, high speed with full-voltage swing without using extra elementary growth on design. In the ﬁrst design, hybrid logic style is employed with 12 transistors. The hybrid logic style utilizes dynamic change in the width Length ratio in order to get specified results new full adders with new methodology. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate- Diffusion-Input) technique in its structure with 12 transistors; it provides high speed and Ultra Low-Power, as well as a full voltage swing without any extra component required. Many of the previously reported adders in literature suffered from the problems of extra elements required to full-fill the circuit recruitment like voltage-swing and speed when operated at low supply voltages. These two new designs successfully operate at ultra low voltages. The studied circuits are optimized at 45nm and 90 nm PTM (Tanner). The comparison between these two novel circuits in terms of Power, Delay and Power-Delay-Product (PDP)
Full adder circuit can be implemented with different combinations of XOR/XNOR modules and two multiplexer but this approach has not been used in current work as XNOR/XOR cell shows high power consumption than single XNOR gate. Proposed full adder circuit has been implemented by two XNOR gates and one multiplexer block as shown in Figure 4. Sum is generated by two XNOR gates and Cout is generated by two transistors multiplexer block. The single bit full adder using proposed XNOR gates with eight transistors has been implemented and shown in Figure 4. For multiplexer section typical values of width (Wn & WP) 0.23µm & 0.23µm for NMOS and PMOS transistors have been taken with gate length of 0.9µm. Simulations have been performed using SPICE based on SAE( Simulation and Analysis Environment) 0.9µm CMOS technology with supply voltage of 1.2V.
In this proposed adder the two transmission gates are used as multiplexer and the sum can be generated by XOR gates and output carry can be generated by XOR /XNOR gates shown in the above figure and output of XOR gate can be used as the selection line for multiplexer or as the control for the transmission gate which we will get output as the carry. The proposed adder circuit is designed by the combination of the two logic styles in order to get lower power consumption, high speed and good energy efficiency. We know that supply voltage variations will leads to the greater reduction in the power and also in the circuit delay.
optimized design is desirable having less numbers of transistors, small power consumption and adequate output voltage swing. Here, in present work a new XNOR gate with three transistors has been proposed. A single bit full adder having eight transistors based on proposed XNOR module and one multiplexer block having two transistors has been presented. The rest of paper is organized as follows: In Section II, a new three transistors XNOR gate has been reported and single bit full adder circuit based on XNOR gates and multiplexer has been designed. In section III results of proposed XNOR cell and single bit full adder designed in previous section have been presented and compared with previous reported circuits. Section IV concludes the work.
ABSTRACT: Programmable Logic Controllers or PLC, normally a digitized controller is fixed, rigid and industrial digital computer. Earlier days in industry, electromechanical relays, timers, counters and sequencers were widely used. The drawback of using these are many with respect to cost, wiring, and maintenance is more. The advancement in PLC came up to overcome all these factors. The question why PLC is the tool, which gives the control and hold in automation, it provides high gain, improved quality and accuracy, works flexible in criticized and hazardous situation, increase product rate, early time to market, low cost, and mainly since the automation helps in designing and changing over easily from one product to another. In this work, we have designed and simulated the basic gates and compound gates using ladder diagram in PLC, using Indraworks, Indralogic platform. This paper forms a basic for designing complex sequential circuits and helps in developing VLSI circuits. This paper gives a overview of AOI(And OR Inverter) and OAI(Or And Inverter) circuits designed and simulated through PLC with the help of ladder diagram .
In 1967 floating gate is firstly introduced and it has non volatile memory. The floating gate transistor used for memory storage application for long period. Now these days in standard CMOS process floating gate transistors are used widely. It has two gates, first is called control gate lying on the top and second gate is isolated called floating gate lying below the control gate . Charge cannot move inside the floating gate without an external force it it is the potential well. Floating gate is the heart of all non volatile memories. It is used independent of external condition in memory cell and changes state from programmed to erased .Threshold voltage of floating gate memory can be calculated as
In this paper, the low power and fast FA circuits are designed by using XOR and XNOR gates. This work presents low power consumption of a 1-bit FA design in 90nm technology. The proposed FA circuits occupy less space due to number of transistors which consumes less power and which is operated at high speed when compared to the convectional FAs. The proposed FA1 circuit has been implemented by removing the P7 and N8 transistors which in turn reduces the circuit complexity. Similarly, in the proposed full adder 2 circuit is implemented by removing the P5 and N7 transistors which in turn reduces the circuit complexity. Similarly, in proposed FA 2 circuit is implemented by removing P5 and N7 transistors. As we on scaling down the transistors lengths to nano scale technologies we can reduce the power consumption from mW to μW. The sizes of all the transistors of proposed full adders are optimized in such a way that it shows low power and high speed, which is suitable for high performance ALUs.
The XNOR-XOR circuit by using CMOS transistor and compare it with the proposed design of XNOR-XOR circuit using transmission gate with CMOS inverter circuit. Figure-1 shows the XNORXOR combine gate using CMOS transistor circuit. There are total sixteen transistors used in which 8transistors are PMOS and rest are the NMOS transistors. The NMOS transistor can give the “LOW” signal completely, but it has very poor performance at “HIGH” signal. Similarly PMOS transistor can gives the “HIGH” signal completely, but poor performance at “LOW” signal .
replaced by the Y and Yˊ , respectively. In the process of designing balanced 3- input XOR–XNOR circuits, we face three independent inputs and two complementary outputs. The result of applying the reduction rules and the substitution and disjoining to the trees.
While designing a processor, high speed processing and low area design are the two key factors of concern in today’s era. It is a well-known fact that a multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures have become the need of the day. In this paper, we have introduced urdhawa multiplier, which is considered to be the fastest multiplier because of its feature of parallel calculation. Also, three designs for Urdhawa Multiplier are further developed and described. In first design, 5:3 compressors based on full adder and utilization in term of 42 delays and 21 areas is developed. In second design we have developed 5:3 compressors based on XOR gate and utilization in term of 36 delays and 24 areas. In third design we have developed 5:3 compressors based on full adder and utilization in term of 28 delays and 18 areas. All the designs and experiments were carried out on Xilinx Vertex-7 series of FPGA and the timing and area of the design on the same have been calculated.
Power consumption and delay are two important considerations for VLSI system designer engineers. Our prime motive is to reduce the power and to get less delay that is nothing but the high speed for any design. Adder is one of the fundamental block present in arithmetic logic unit (ALU), floating point unit .In present arena we need fast arithmetic computation cells like adder and multipliers in the very large scale integration (VLSI) designs. The XOR/XNOR is the basic building block in many circuits like Arithmetic circuits.
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The proposed XNOR-XOR cell based 2x2 array multiplier has been compared with 2x2 array multiplier using existing XNOR-XOR cell in terms of power consumption and power-delay product at varying input voltage, temperature and frequency. All pre-layout and post-layout simulations have been performed on Tanner EDA tool version 12.6 at 45nm technology with input voltage ranging from 0.6V to 1V in steps of 0.1V. The proposed design improves power consumption and PDP which is of great interest in the complex circuit design. Hence this proposed design acts as better option to be used in power efficient complex systems with optimum performance.
848 | P a g e RCA block has these four sub-blocks: half sum generator (HSG) unit, half carry generator (HCG) unit, full sum generator (FSG) unit and full carry generator (FCG) unit. The HSG block generates sum and carry output using the conventional half adder circuit using the corresponding bits of the CSLA. It consists of N numbers of XOR gates and AND-gates to perform the operation.
In a nutshell, our protocol consists of doing cut-and-choose of independently garbled gates and wire authenticators, which are then soldered together into fault tolerant buckets, which are again soldered together into a fault tolerant circuit. Robustness is guaranteed by ensuring a combined majority of correct gates and correct wire authenticators for each bucket. In other words, if the gates of any bucket disagree on the output key (after soldering) then the attached wire authenticators are invoked and the key which is output/accepted by a majority of both gates and wires will be chosen as output key. As wire authenticators are lighter than gates, in terms of computation and communication, we get a significant increase in performance over MiniLEGO where buckets only consisted of gates. We start by giving an informal description of the elements of our garbling scheme, while in Section 6.1 we show the full details of our scheme and prove that it meets the requirements of an interactive garbling scheme. Setup B starts by committing, using the commitment scheme F COM , to his challenges for the cut-and-choose
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We functionally verified each unit presented in this paper including all three 4:2 Compressor, 7:2 Compressor, Compressor based Urdhwa multiplier. We have been found from the results shown in Table 3 respectively, that number of slices used is same in case of 4:2 compressor based on Full adder and 4:2 compressor based on XOR gate which is less than slices used in 4:2 compressor based on XOR-XNOR gate.