• No results found

[PDF] Top 20 Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device

Has 10000 "Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device" found on our website. Below are the top 20 most common "Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device".

Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device

Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device

... FPGAs have a high capability to accelerate computer algorithms due to the parallel decomposition characteristics of some of them. This section shows the computer algorithms that are not enclosed in the previous sections. ... See full document

111

Abstract: Using the Field Programmable Gate Array (FPGA) based Embedded Systems (ES) for signal

Abstract: Using the Field Programmable Gate Array (FPGA) based Embedded Systems (ES) for signal

... the Field Programmable Gate Array (FPGA) based Embedded Systems (ES) for signal processing purposes, gives rise to the need to equip the FPGA of a Bluetooth (BT) connectivity if ... See full document

9

Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

... the Field Programmable Gate Array (FPGA) implementation of fixed width standard and truncated multipliers using Very High speed integrated circuit Hardware Description Language and ... See full document

5

An Efficient Implementation of Matrix Multipliers for signal Processing on FPGA

An Efficient Implementation of Matrix Multipliers for signal Processing on FPGA

... and Field Programmable Gate Array (FPGA) implementation of matrix multiplier architectures for use in image and signal processing ...Virtex-4 FPGA and the performance is ... See full document

5

FPGA based IP cores implementation for face
recognition using dynamic partial reconfiguration

FPGA based IP cores implementation for face recognition using dynamic partial reconfiguration

... Abstract This paper presents a combination of novel feature vectors construction approach for face recognitionusing discrete wavelet transform DWT and field programmable gate array FPGA-[r] ... See full document

14

Implementation of Direct Sequence Spread Spectrum Communication System Using FPGA

Implementation of Direct Sequence Spread Spectrum Communication System Using FPGA

... by Field Programmable Gate Array (FPGA) for baseband spread spectrum communication system using Pseudo Noise Sequences (PNS) for spreading digital ...(BER), Field ... See full document

9

Universal Time And Calendar System In Field Programmable Gate Array (FPGA)

Universal Time And Calendar System In Field Programmable Gate Array (FPGA)

... after device manufacturing. The FPGA generally used with the hardware description language to specify the ...a general-purpose hardware description language same as the C ... See full document

24

Implementation of Cryptography Algorithms in Field Programmable Gate Array

Implementation of Cryptography Algorithms in Field Programmable Gate Array

... security field, the tested FPGA device is described in its own chapter, the design and completed solution and the results of systematic tests has presence at the end of this ... See full document

6

Three Bit Subtraction Circuit Via Field Programmable Gate Array (FPGA)

Three Bit Subtraction Circuit Via Field Programmable Gate Array (FPGA)

... using FPGA board by using Verilog language. A FPGA is a semiconductor device containing programmable logic components called "logic blocks", and programmable ... See full document

24

FIELD PROGRAMMABLE GATE ARRAY

FIELD PROGRAMMABLE GATE ARRAY

... Field-programmable gate arrays (FPGAs) arrived in 1984 as an alternative to programmable logic devices (PLDs) and ...with FPGA development, logic design begins to resemble ... See full document

15

High speed FPGA model implementation for ferroelectric and ferromagnetic transducers operating in hysteretic regimes

High speed FPGA model implementation for ferroelectric and ferromagnetic transducers operating in hysteretic regimes

... code to be compiled directly from Simulink to the FPGA without the need to manipulate or interconnect anything in VHDL or Verilog. This board contains two Xilinx Virtex II 3000 FPGAs as well as four Texas ... See full document

20

GSM remote sensing for transmission line monitoring system using FPGA

GSM remote sensing for transmission line monitoring system using FPGA

... 8 mobile phone. It is composed of the mobile phone, MCU, GSM module and relays. The smart wireless remote communication between user and homes is realized by GSM network. The advantages of the system, the controller can ... See full document

40

Application of FPGA in high speed CMOS digital image acquisition and color recognition system

Application of FPGA in high speed CMOS digital image acquisition and color recognition system

... original programmable gate device limited number of ...of FPGA in high-speed CMOS digital image acquisition and color recognition ...chip FPGA, it is the imaging system components, ... See full document

8

The design of an FPGA-based sinusoidal pulse width modulation generator

The design of an FPGA-based sinusoidal pulse width modulation generator

... Most modern AC variable speed drives are based on power electronic switches which can be turned ON and OFF by low power control circuits connected to their control gates. Also, many microcontrollers and digital signal ... See full document

22

Cataract Detection

Cataract Detection

... With this design approach the distinctive features of using programmable digital devices are reached.Repeating a design consists in reprogramming the FPGA in thechosen board. The design and simulation times ... See full document

7

FPGA-Based Flash Memory Controller for BZK.SAU.FPGA10.1 Microcomputer Architecture Design as an Educational Tool

FPGA-Based Flash Memory Controller for BZK.SAU.FPGA10.1 Microcomputer Architecture Design as an Educational Tool

... For writing data to flash memory we should process program command consists of four cycle shown in Table IV. After processing the first three cycle the device is ready for writing data. In the fourth cycle we ... See full document

5

Dataflow Computer Architecture Generator using Field Programmable Gate Array

Dataflow Computer Architecture Generator using Field Programmable Gate Array

... The paper introduces dataflow computing paradigm, which is driving the computation process with the flow of data, not with the flow of instructions, as control flow computers are doing. Static, dynamic and hybrid data ... See full document

5

U Tube Manometer Calibration using ANFIS

U Tube Manometer Calibration using ANFIS

... Fig 3: Block Diagram for U-tube Manometer Calibration U-Tube manometer has a non-linear relation between the capacitance developed by changing the level of mercury and the level of mercury. Since the frequency produced ... See full document

5

FPGA Implementation of Peak Detector, 64 Bit BCD Counter and Reset Automatic Block for Pd Detection System Using VHDL Simulation
P Sateesh Kumar, M Kesab Chandrasen, V Suresh & V Ravi Tejesvi

FPGA Implementation of Peak Detector, 64 Bit BCD Counter and Reset Automatic Block for Pd Detection System Using VHDL Simulation P Sateesh Kumar, M Kesab Chandrasen, V Suresh & V Ravi Tejesvi

... The counter starts to count PD Signal when the CE (Chip Enable) is high or Active. If the data of ADC signal is more than 8Fh or 2.8 Volt then the counter will detect data and increase counting, but if the data of ADC ... See full document

8

Subtraction And Addition Design Using Field Programmable Gate Array (FPGA)

Subtraction And Addition Design Using Field Programmable Gate Array (FPGA)

... Figure 2.4: 16-Bit Composed of 4-Bit Adders Linked by Ripple Carry Propagation This literature review is about designing High-Speed adders especially in Semi- Custom designs because the technique that is used in the ... See full document

24

Show all 10000 documents...