[PDF] Top 20 EFFICIENT FAULT DETECTION CODES
Has 10000 "EFFICIENT FAULT DETECTION CODES" found on our website. Below are the top 20 most common "EFFICIENT FAULT DETECTION CODES".
EFFICIENT FAULT DETECTION CODES
... cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of ...proposed fault-detection ... See full document
13
An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]
... of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is ...stuck-at fault in the interconnect ... See full document
8
Efficient error detection codes for multi code upset correction in SRAM based FPGA
... There are also a few schemes to specifically address MBUs in FPGA devices. In addition, Xilinx offers a soft error mitigation controller (IP block) based on cyclic redundancy code (CRC) and ECC which can correct up to ... See full document
6
Smart Fault Detection and Home Automation System
... smart fault detection to ensure the security parameters of the ...provide fault detections in order to increase the security of the house and also make the household appliances to work with just a ... See full document
8
Efficient Cluster based Fault Detection and Recovery in Wireless Sensor Network
... it efficient optimization for RTP is done and finds that Discrete RTP is optimized analysis time is low compared to ...linear. Fault node present in the network is efficiently identified by calculating RTD ... See full document
7
Efficient Fault Detection and Dyad Routing Algorithm for 3D Network on Chip
... the fault in the NOC ...the fault and the data sent to the ...without fault occurrence. To implementing the DyAD algorithm and fault detection method in NOC design ,we have to get ... See full document
6
Energy Efficient Fault Tolerant Sensor Node Failure Detection in WSNs
... node detection techniques are mainly affected due to energy consumption of sensor nodes in ...energy efficient fault tolerant sensor node failure ...WSNs. Fault tolerance is achieved by ... See full document
12
An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications
... he reliability of memories depends on dimensions of the circuit, operating voltages, and integrated density Triple modular redundancy codes and error correcting codes are mostly used for error correcting. ... See full document
5
Efficient test compaction for combinational circuits based on Fault detection count directed clustering
... In order to increase the level of compaction, FCC can be applied in an iterative manner until no compaction improve- ment is possible. We have experimented with an iterative version of FCC, called FCC6þ, by applying FCC ... See full document
5
Detection of Faulty Sensors in Wireless Sensor Networks and Avoiding the Path Failure Nodes
... automated detection and identification of sensor faults must be an integral part of their design and operation, especially for applications where the monitoring system is unattended after ...energy ... See full document
6
Machine Learning as an Efficient Diagnostic Tool for Fault Detection and Localization in Solar Photovoltaic Arrays
... We need to ascertain whether there is an open-circuit when there is any change in the current sensors: usually its measurements will be ~0 in that branch. Figure 10 depicts the current-voltage (I-V) curve of 8x3 PV array ... See full document
13
On Evaluating Fault Resilient Encoding Schemes in Software
... the fault does not propagate in all the cases, such as Safe-Error Analysis or Ine ff ective Fault Analysis (recently utilized in ...stuck-at fault model, ...the fault value. Therefore, any ... See full document
18
An efficient fault detection algorithm for buck converter fed BLDC motor drive
... other fault tolerant control methods, the parameter selection plays a crucial ...The fault control method for the buck converter fed BLDC motor drive system with protective circuit discussed in the paper is ... See full document
15
Multi Fault Detection and Correction Using Error Correction Codes and Parseval Checks
... the detection of all errors ...implementation, fault injection experiments should be done to determine the percentage of errors that are actually ... See full document
8
Simultaneous fault models for the generation of efficient error detection mechanisms
... Table II demonstrates levels of efficiency commensurate with those previously observed when using decision tree induction and rule induction algorithms to generate error detection predicates [10]. The hallmarks of ... See full document
13
Fault Detection and Soft Errors Correcting Codes Using Parallel FFT
... The proposed system is simulated in ModelSim SE 6.3f. A model of the communication channel is formed. In communication channels the bandwidth will be high. So the FFTs will have large inputs. This project is used for ... See full document
8
High Speed Fault Tolerant Parallel Ffts Using Error Correction And Detection Codes
... The TMR, which triplicates the design and adds voting logic to correct errors, is commonly used. However, it more than triples the area and power of the circuit, something that may not be acceptable in some applications. ... See full document
5
Efficient Bio inspired Method for Disaster Monitoring in Wireless Sensor Networks Using Improved PSO
... Bayesian detection scheme in [9] selects the minimum neighbors for a given detection error bound such that the communication volume is minimized during the fault ...event detection accuracy in ... See full document
7
ASIC Implementation of MLDD for Error Detection and Correction
... [8]. R. Meenaakshi Sundhari, et al proposed an efficient majority logic fault detection to reduce the accessing time for memory applications using the quasi cyclic LDPC codes. Exhaustive ... See full document
8
A Memory Efficient Vlsi Iplementation Of Golay Codes
... Block codes are referred to as (n, k) codes. A block of k information bits are coded to become a block of n bits. n=k + r, where r is the number of parity bits and k is the number of information bits. ... See full document
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