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[PDF] Top 20 Packet Processing on Stream Architecture

Has 10000 "Packet Processing on Stream Architecture" found on our website. Below are the top 20 most common "Packet Processing on Stream Architecture".

Packet Processing on Stream Architecture

Packet Processing on Stream Architecture

... The Imagine Processor consists of 8 clusters and each has a 256-entry, 32-bit word scratch- pad. These scratchpads, as illustrated in Figure 5.2, are good candidates serving as multi-segment memories which provide 65536 ... See full document

143

A Feasibility Study on the application of Stream Architectures for Packet Processing Applications

A Feasibility Study on the application of Stream Architectures for Packet Processing Applications

... Index into the SRAM table with the level information and the extracted four bits of the destination address: The four bits of the destination address and the level information (i.e. the level of the SRAM the ... See full document

105

Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches Adhirai B, Akshaya K, P Prema

Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches Adhirai B, Akshaya K, P Prema

... of packet processing features. The OpenFlow architecture aims to provide elasticity and programmable packet processing to meet these converging ...per-port packet prediction ... See full document

9

Efficient Mitigation Of Ip Spoofing Using Bgp-idpf-cms Architecture

Efficient Mitigation Of Ip Spoofing Using Bgp-idpf-cms Architecture

... further processing. In Path Identification [20], each packet along a path is marked by a unique Path Identifier (Pi) of the ...new packet-marking ... See full document

5

Survey of Distributed Stream Processing for Large Stream Sources

Survey of Distributed Stream Processing for Large Stream Sources

... distributed architecture consisting of Borealis servers running in different sites and these sites are interconnected to take coordinated ...individual processing elements, a storage manager for storing the ... See full document

16

Packet processing engine with firefly scheduling in green networking

Packet processing engine with firefly scheduling in green networking

... location, energy use in buildings housing hardware, or other peripheral aspects of a network infrastructure. Ideas associated with green networking also address tech services or user relationships that may ultimately be ... See full document

6

Survey of Machine Learning Applications

Survey of Machine Learning Applications

... novel architecture for performing machine learning on Big ...Their architecture provides reliable storage on HDFS (Hadoop Distributed File System) and ...This architecture is developed using the ... See full document

8

FPGA Implementation of 3D DCT Requiring Only 14 Additions

FPGA Implementation of 3D DCT Requiring Only 14 Additions

... Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 3D DCT ... See full document

6

An Improved Stream Processing Access

An Improved Stream Processing Access

... IOT architecture are challenging tasks and many researchers are showing interest to build modern Real time cloud and IOT based applications like smart cities, Video mining, Health care, Industrial event monitoring ... See full document

5

Scheduling in distributed stream processing systems

Scheduling in distributed stream processing systems

... Finally, GATES is a grid-based middleware for processing distributed data streams. The design of GATES focuses on extension of the existing Open Grid Services Architecture to allow ecient distributed ... See full document

84

Multiplier Based and Canonical Signed Digit
Based VLSI Architecture for Discrete Wavelet
Transformation

Multiplier Based and Canonical Signed Digit Based VLSI Architecture for Discrete Wavelet Transformation

... proposed architecture of a wavelet packet transforms using parallel ...This architecture increases the speed of the wavelet packet ...word-serial architecture able to compute a complete ... See full document

5

Stateful NAT64: Network Address and Protocol Translation from IPv6 Clients to IPv4 Servers RFC 6146

Stateful NAT64: Network Address and Protocol Translation from IPv6 Clients to IPv4 Servers RFC 6146

... a packet do a "U-turn" inside a NAT and come back out the same side as it arrived ...the packet is being sent to another IPv6 host connected to the same ...a packet is called a ’hairpin ... See full document

45

DATA HIDING USING STEGONOGRAPHY

DATA HIDING USING STEGONOGRAPHY

... Packet loss occurs in every kind of network. All network protocols are designed to cope with the loss of packets in one way or another. TCP protocol, for example, guarantees packet delivery by sending ... See full document

10

AVOIDING PACKET DROP FOR IMPROVED THROUGHPUT IN THE MULTI-HOP WIRELESS N/W

AVOIDING PACKET DROP FOR IMPROVED THROUGHPUT IN THE MULTI-HOP WIRELESS N/W

... The proposed algorithm is being implements using NS2/NS3 simulation environment and it is expected that the results shall be improved. Existing IEEE 802.11 algorithm shall be used to compare in the similar environment ... See full document

7

Design of a Graphical User Interface for Audio Data Acquisition and Stream Processing using Matlab System Objects

Design of a Graphical User Interface for Audio Data Acquisition and Stream Processing using Matlab System Objects

... This Paper aims at describing a project developed using MATLAB® from The Mathworks, Inc, a software development environment used in many electronic fields (e.g. safety systems, motor vehicles, interplanetary spacecrafts, ... See full document

43

Real Time analysis of a multi client multi server architecture for 
		networked control systems

Real Time analysis of a multi client multi server architecture for networked control systems

... MC–MS architecture performed better than other architecture because it could overcome the effects of network load and was unaffected by major packet ... See full document

5

Robust and Traffic Aware Medium Access Control Mechanisms for Energy-Efficient mm-Wave Wireless Network-on-Chip Architectures

Robust and Traffic Aware Medium Access Control Mechanisms for Energy-Efficient mm-Wave Wireless Network-on-Chip Architectures

... a certain number of slots where the number of slots is the number of flits that can be transmitted over the wireless medium. The token is then passed to the next WI as a token flit to allow other WIs to transmit through ... See full document

142

High-radix Packet-Switching Architecture for Data Center Networks

High-radix Packet-Switching Architecture for Data Center Networks

... We further study the scalability and robustness of the MDN- based multistage design under a bursty traffic, by varying the architectural settings. We investigate the effect of speedup, load, on-chip buffers capacity, ... See full document

7

A Priority based SRM Algorithm for VOQ Packet Switch Architecture

A Priority based SRM Algorithm for VOQ Packet Switch Architecture

... Virtual Output Queuing (VOQ) is used to overcome the head-of- line (HoL) blocking problem in input-queued (IQ) packet switches. There are a lot of research has been devoted to design iterative arbitration ... See full document

6

AN IMPROVED ARCHITECTURE FOR MINIMIZING REAL TIME PACKET LOSS IN MIPV6

AN IMPROVED ARCHITECTURE FOR MINIMIZING REAL TIME PACKET LOSS IN MIPV6

... proposed architecture suggests the solution to the problem of packet loss that occurs in the existing ...Proposed architecture suggests the use of the buffering mechanism to minimize the ... See full document

7

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