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high-performance system-on-a-chip design

A High Performance System on Chip Bus Design and Verification

A High Performance System on Chip Bus Design and Verification

... A universal asynchronous receiver/transmitter, abbreviated UART is a computer hardware device translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication.A UART is usually ...

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Component-based Specification for Multi-Processor System-on-Chip Design

Component-based Specification for Multi-Processor System-on-Chip Design

... allow high performance and low power design, while keeping the time-to-market short enough for consumer’s ...overall design time demanding a design automation from the user-level ...

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A Study on Network-On-Chip architecture using Genetic Algorithm

A Study on Network-On-Chip architecture using Genetic Algorithm

... new design methodology results in increase in performance over conventional bus ...and high power consumption, which can be solved by GA optimization ...

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Virtual Platforms in System-on-Chip Design

Virtual Platforms in System-on-Chip Design

... the design teams, although many use one or two. The high-level platform is useful for algorithms developers, who implement new algorithms or optimize existing ones; it can also serve as a functional ...

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A lightweight RSA based System on a Chip Design for Constrained Application

A lightweight RSA based System on a Chip Design for Constrained Application

... electronic system into a single chip is called a ...a system integrator can select from with relevant documentations on power, timing and ...The design of SoC is categorized into two based on ...

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A System on a Chip Design of the AES Cryptographic System

A System on a Chip Design of the AES Cryptographic System

... Synopsys Design Compiler using the 180nm TSMC cell ...a high throughput needed for the fast propagation of ...the design was ...cryptographic system can be applied to resource constrained ...

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A High Performance Modified AXI Master Slave on Chip Bus Design and Verification

A High Performance Modified AXI Master Slave on Chip Bus Design and Verification

... “A High-Performance Modified AXI Master Slave On-Chip Bus Design and Verification” Proposed a high- performance system-on-chip bus ...a high-throughput ...

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Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

... on- chip bus is an established, open specification that serves as a framework for System- on-chip (SoC) ...two system buses: the Advanced High performance bus (AHB) and the ...

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Design and Optimization of System-on-chip (SOC)

Design and Optimization of System-on-chip (SOC)

... of high-performance embedded platforms that can handle the computational requirements of recent complex algorithms, which cannot be executed in traditional embedded mono- processor ...low-power, ...

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A High Performance Clock Distribution Network for System on Chip

A High Performance Clock Distribution Network for System on Chip

... the design of the clock distribution network represents the fundamental circuit- based performance limitation in high-speed synchronous digital ...inthe design, analysis, and evaluation of ...

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System on Chip Design Using High Level Synthesis Tools

System on Chip Design Using High Level Synthesis Tools

... PICO design tools to their FPGA flow, designers can create complex hardware [20] sub-systems from se- quential untimed C ...programmability, performance, power, area and clock ...

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A Review on the Performance Analysis of VCR System Using Nanorefrigerants

A Review on the Performance Analysis of VCR System Using Nanorefrigerants

... at high temperature and high ...refrigerator system was familiar solvents and volatile ...refrigeration system, propane (R-290) was marketed in replacing ammonia (R-717) as refrigerant ...

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The study of chaos encryption algorithm for wireless sensor networks based on the reconfigure technology of FPGA

The study of chaos encryption algorithm for wireless sensor networks based on the reconfigure technology of FPGA

... systems design funded by the national project design ...EEPROM chip to store programs and data. ESB node system also used the MSP430 MCU of IT company as microcontrollers and used RFM TR1001 ...

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Design of a high pressure reaction system and the uncatalyzed high pressure oxidation of pseudocumene by sulfur dioxide.

Design of a high pressure reaction system and the uncatalyzed high pressure oxidation of pseudocumene by sulfur dioxide.

... reaction system was to be designed which would be s u f f i ­ c ie n tly general in design as to permit the study o f various reactions under high ...

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Amphenol Docking Connectors

Amphenol Docking Connectors

... Expert design and applications engineering provides solid modeling and full Pro-E capabilities to develop new interconnect products and perform structural ...

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FPGA Design of Speech Compression by Using Discrete Wavelet Transform

FPGA Design of Speech Compression by Using Discrete Wavelet Transform

... First, PC plays speech signal. At the same time, FPGA ADC controller starts sampling the ADCDAT signal sent from the WM8731 codec, and stores each left channel sample into the SDRAM chip. This design work ...

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The SA601: The First System-On-Chip for Guitar Effects By Thomas Irrgang, Analog Devices, Inc. & Roger K. Smith, Source Audio LLC

The SA601: The First System-On-Chip for Guitar Effects By Thomas Irrgang, Analog Devices, Inc. & Roger K. Smith, Source Audio LLC

... The SA601 is a mixed signal device fabricated in 0.18u CMOS. The product is housed in a tiny 48 pin surface mount package. It is manufactured by Analog Devices, Inc., one of the leading mixed signal semiconductor ...

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Coupled Chip-to-Chip Interconnect Design

Coupled Chip-to-Chip Interconnect Design

... dedicated high voltage power ...The high edge rate provided by 90nm CMOS enables a ...receiver design, the power consumption is independent with the data ...

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Design and Implementation of Real Time Data Acquisition System in All Programmable System on Chip

Design and Implementation of Real Time Data Acquisition System in All Programmable System on Chip

... Obviously, SoC structures are huge, complex plans that require broad testing and confirmation. To accomplish this, the item advancement procedure must guarantee the item determination stage is coordinated easily with the ...

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Design and Analysis of On-Chip Router for Network on Chip

Design and Analysis of On-Chip Router for Network on Chip

... Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin and Yu- Hen Hu et. al [3] addresses the buffer utilization by making the channels bidirectional and shows significant improvement in system performance. But in ...

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