low-voltage CMOS technology
A Linear CMOS Low Drop-Out Voltage Regulator in a 0.6μm CMOS Technology
... The gain, phase and output swing of the designed opamp were obtained using some simulations. For AC simulation a 2pF load capacitor was used. The gain and phase response of the opamp have been shown in Fig. 3. The gain ...
6
Gain and Bandwidth Enhancement in CMOS Low Voltage Low Power Operational Amplifiers
... a low-voltage low-power CMOS operational amplifier using the composite cascode technique is ...μm CMOS technology, to evaluate the proposed ...the low supply ...
7
Voltage Level Shifter Circuits in 45nm CMOS Technology A Review
... source voltage (Vgs) of transistor Q3 and transistor Q4 supply latching voltage on node A1 and ...This voltage is used for cross coupled transistors Q1 and Q2 to create a positive feedback action ...
6
Design of Low Voltage CMOS OTA Using Bulk - Driven Technique
... dependable low voltage and low power amplifiers ...the CMOS technologies there are some drawbacks of the bulk-driven technique like the value of g mb will be 5-8 times smaller than the value ...
9
A STUDY OF LOW TO HIGH SWING CONVERTERS FOR ON-CHIP INTERCONNECTS IN CMOS VOLTAGE INTERFACE CIRCUITS
... 76 | P a g e insertion techniques effectively improve the data rate for long on-chip interconnects by changing the quadratic relationship between line delay and line length to a linear relationship (Figure 1.1). Up to ...
9
circuit. T designin analog c using 18 56.88% low volta range of
... supply voltage and channel length scale down with the advancement of new generation CMOS ...mode voltage and reduces the harmonic distortion. The realization of CMOS based OTA has resulted in ...
9
An Efficient Design of Adder using Ultra Low Voltage CMOS Logic
... supply voltage should yield even greater benefits. Reducing the supply voltage is the key to low- power operation, even after taking into account the modifications to the system architecture, which ...
9
Design of Low Power Low Voltage Circuit using CMOS Ternary Logic
... In new technologies, most delay and power occurs in the connection between gates. When designing a function using Ternary logic or Multiple valued logic, need less gates, which implies less number of connections and the ...
8
Efficient Implementation of Low Power CMOS Voltage Controlled Oscillator in PLL
... for low power ...of low power CMOS VCO circuitry with the frequency range from 3GHz - 6GHz and reducing the power dissipation up to 20-25% by applying some low power techniques like Power ...
8
Design of Voltage Controlled Oscillator in 180 nm CMOS Technology
... sources, M13 and M14, limit the current available to the inverter M1 and M2. In other words, the inverter is starved for the current. The MOSFETs M11 and M12 drain currents are the same and are set by input control ...
6
A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer
... M. Zareie was born in Hamadan, Iran in 1992. She received the B.Sc. degree in Electrical Engineering from Buali-Sina University, Iran, in 2014 and currently she is the M.Sc. student of Electrical Engineering at Iran ...
11
A Power Efficient CMOS PLC Receiver Design-Dual Use of Power Lines for Design for Testability
... .18µm CMOS technology under a supply voltage of ...like low data rate communications ...supply voltage and ...a voltage drop of up to ...
8
A Subthreshold Low Voltage Low Phase Noise CMOS LC VCO with Resistive Biasing
... a low- phase-noise LC-VCO is designed using resistive biasing instead of active current source ...for low-phase-noise and low-voltage operation because of its inherent advantage of low ...
7
A low power, low cost infra red emitter in CMOS technology
... commercial CMOS process for fabrication, with [16] using polysilicon as a heater material, and [17] using a single-crystal silicon heater with aluminium to form electrical connections between the heater and ...
10
Design of a Programmable Low Drop-Out Regulator using CMOS Technology
... of low drop-out regulator by applying different ...nm technology proves better in achieving required performance ...of low voltage, low-dropout regulators can be ...response, low ...
7
A New Approach for Low Voltage CMOS based on Current-controlled Conveyors
... the low voltage circuits became necessary for operation in modern systems like battery supply or portable ...in low voltage because of utilizing all of voltage ...(CMOS) ...
8
Low voltage CMOS Schmitt Trigger in 0.18 m technology
... proposed CMOS Schmitt Trigger circuit which is capable to operate in low voltage ...supply voltage is an effective method to achieve low power operation ...
8
Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
... the CMOS technology is continuously scaling down, the design of ultra-high speed wired or wireless communication system is becoming ...digital CMOS technology a challenging aspect for analog ...
8
An Improved Low Power, High Speed CMOS Adder Design for Multiplier
... improved CMOS full adder circuit for high speed and low power applications is proposed in this paper at 90 nm technology node with supply voltage ...
5
A REVIEW OF LOW POWER FLASH ADC USING THRESHOLD INVERTER QUANTIZATION TECHNIQUE
... 3-bit CMOS flash ADC utilizing Threshold Inverter Quantization technique” Kalpana Chaudhary, ...cascaded CMOS inverters as a ...in technology, digital signal processing has gained significant ...
11