pass-transistor-based logic
Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime
... CMOS logic style such as pass transistor logic, transmission gate and gate diffusion input (GDI) using with stacking power gating leakage reduction ...CMOS logic style. On the basis of ...
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Low Power 32-bit Improved Carry Select Adder based on MTCMOS Technique
... ABSTRACT: The raise in requirement for mobile and electronic devices is causing the necessity of low power. This paper presents the design of Carry Select Adder using MTCMOS technique. A 32-bit CSA is designed. The ...
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Low Voltage and Low Power Divide-By- 2-3 Counter Design Using Pass Transistor Logic Circuit Technique
... A state-of-the-art divide-by-2/3 counter design is given in Fig. 1(a) [7]. It contains two E-TSPC-based FFs and two logic gates i.e., an OR gate and an AND gate. When the divide control signal DC is “0”, ...
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Comparative Performance Analysis of XOR - XNOR Function Based High - Speed CMOS Full Adder Circuits
... Logic Design and XOR-XNOR Design in a single unit. The main motive of this paper is to determine the comparative study of power, delay, power delay product (PDP) of different Full adder designs using CMOS ...
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Design and Implementation of Efficient Adder using Various Logic Styles
... different logic styles such as pass transistor logic, mux- based logic, and 2T ...a logic circuit using multiple full adders to add N-bit ...
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A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors
... The quantitative analysis of number of transistors, delay, power dissipation and PDP are shown in Table I and Table II. This table shows that the delay of the proposed 5T Ex-OR/Ex-NOR gate is lesser than the circuit ...
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Implementation of Modified Baugh Wooley Signed Multiplier
... conventional logic gates/cells, based on complementary pass transistor logic and have been validated with simulations, a layout ...
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Design of Parallel in Parallel out Shift Register using Clocked Pass Transistor Logic
... To evaluate the performance, Shift Registers discussed in this paper are designed using 90-nm CMOS technology. All simulations are carried out using MICROWIND simulation tool at nominal conditions with 1GHz frequency ...
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Low Power Full Adder With Reduced Transistor Count
... is based on complementary pull up and pull down ...[4] based on simultaneous XOR-XNOR signals is an improvement from 14T full ...is based on CMOS transmission gates and CMOS ...Complementary ...
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Design of Double Tail Comparator Using Dual Mode Logic in PTL Design
... comparator based on dual mode logic in pass transistor logic design to achieve low power and high performance and shows comparison between optimization of delay between ...in ...
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LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC
... Pass transistor logic is used to improve the performance of arithmetic and logic ...This logic can be used to reduce the power dissipation in the system and to increase the speed of ...
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Low Power High Speed Full Adder based on Pass Transistor Logic
... Fig.2 shows the design of the proposed full adder. The XNOR block is used to implement the sum output of the full adder. There are two transistors Mp1 and Mn1 present within the inverter which helps in the generation of ...
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Design the 2X1 MUX with 2T Logic and Comparing the Power Dissipation and Area with Different Logics
... combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control ...and pass-transistor logic ...compared ...
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IMPLEMENTATION OF COMPLEMENTARY PASS TRANSISTOR LOGIC FOR LOW POWER MULTIPLY AND ACCUMULATE CIRCUIT
... low-power logic circuit technique, is used for many VLSI ...restored pass-transistor logic network which is introduced here in this paper is used to perform logic ...SRPL based ...
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Analysis and Design of Low Power Arithmetic Circuits
... is based on the number of transistors ...MUX based adder, pass transistor and 2-T logic our project is mainly depends on Gate Diffusion ...
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Design Of Pulse Triggered Flip Flop And Analysis Of Average Power
... architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these ...design based on a signal feed-through ...simple pass transistor ...
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1. Design of low power and high speed multiplier
... The synthesis result confirms that the proposed multiplier is suitable for low power and small area applications[10]. The Speed enhancement and lower power consumption was achieved by replacing the conventional full ...
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Design of ALU Based on Reversible Gates
... reversible logic gate should follow property of bijection between input and ...classical logic gate, reversible logic gate can be designed by using pass transistor as given in [6] or ...
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High Speed Tree based 64 Bit Binary Comparator using New Approach
... Hence, modified pass transistor logic style is employed to reduce the number of transistors up to 9 (including inverters). In above 8-bit example circuitry, the first stage comparison circuit ...
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LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING
... Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS ...sleep transistor is added between actual ground rail and ...
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