Viterbi Decoder
Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog
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Hybrid Architecture for OFDM with Optimized Design of Analog Viterbi Decoder
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Interleaved Convolutional Code and Its Viterbi Decoder Architecture
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A Novel High Speed Configurable Viterbi Decoder for Broadband Access
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Speed and Power Optimization of FPGA'S Based on Modified Viterbi Decoder
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Design Approach of High Speed Parallel Processed Viterbi Decoder with Pipelining Technique
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Typical Implementation of VITERBI Decoder for efficient error detection and correction
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LOW POWER VITERBI DECODER FOR TCM USING T-ALGORITHM
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Optimum Viterbi Decoder Design and its Implementation on FPGA
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Performance and Analysis of Viterbi Decoder Using VHDL
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Design of Asynchronous Viterbi Decoder Using Pipeline Architecture
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Implementation of Dual Booting Module of Convolution Encoder and Viterbi Decoder
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IMPLEMENTATION OF EFFICIENT CONVOLUTIONAL ENCODER AND MODIFIED VITERBI DECODER
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Implementation of Adaptive Viterbi Decoder on FPGA for Wireless Communication
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Power Efficient Survivor Memory Architecture for Viterbi Decoder
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Low-Power Adaptive Viterbi Decoder for TCM Using T-Algorithm
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Design and Implementation of High Speed Low Power Viterbi Decoder
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The Design of Viterbi Decoder with Higher Efficiency
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Implementation of Adaptive Viterbi Decoder
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Implementation of Convolution Encoder and Viterbi Decoder
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