[PDF] Top 20 Advanced Gate Stacks for Strained Si Devices
Has 10000 "Advanced Gate Stacks for Strained Si Devices" found on our website. Below are the top 20 most common "Advanced Gate Stacks for Strained Si Devices".
Advanced Gate Stacks for Strained Si Devices
... Intel demonstrated strained silicon MOSFETs with uniaxial strain based on the structure shown in Figure 1-7[39, 40]. Piezoresistance coefficients in silicon were used to model the behavior of uniaxial stress in ... See full document
195
Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices
... for gate injection is larger than for an accumulated substrate for substrate injection; ~ ii ! the voltage drop for a depleted or inverted polysilicon contact for substrate injection is larger than for accumulated ... See full document
11
Modelling of advanced submicron Gate InGaAs/InAlAs pHEMTS and RTD devices for very high frequency applications
... and Advanced Design System (ADS) to appreciate the underlying device physics of the device towards the device output characteristics, to reproduce both the DC and RF device characteristic, and investigate the ... See full document
53
Spectroscopic Study of the Interface Chemical and Electronic Properties of High-kappa Gate Stacks
... The internal interfaces of the gate stack will significantly affect the performance of the devices. Chemical bonding occurs at these interfaces and the charge transfer across these bonds can result in an ... See full document
162
Electronic Defect Characterization of Strained-Si/SiGe/Si Heterostructure
... bulk Si in high-speed complementary metal-oxide-semiconductor (CMOS) technology, due to the higher electron and hole mobilities in the strained-Si channel layer ...the strained-Si ... See full document
109
Compressively strained, buried channel $Si {0 7}$Ge$ {0 3}$ p MOSFETs fabricated on SiGe virtual substrates using a 0 25 µm CMOS process
... as-drawn gate length around 0.2 µm smaller than some of the other devices in the same plot and demonstrates one of the disadvantages of the buried channel design in that the gate has less control of ... See full document
7
Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity
... for Advanced Electronic Materials Process- ing, the Office of Naval Research, the Air Force Office of Scientific Research, the Semiconductor Research Corpora- tion, SRC, and the SRC/Sematech Center for Front End ... See full document
9
Interfacial strain-induced self-organization in semiconductor dielectric gate stacks. I. Strain relief at the Si-SiO2 interface
... The density of dangling bond defects prior to the PMAs, but after thermal annealing at 900 °C, is approximately constant and in the low 10 12 cm ⫺ 2 regime. It is independent of the way a device quality interface is ... See full document
10
Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs
... of Advanced Micro Devices, Austin Texas, where I interned as a process development engineer for strained Si ...using advanced simulation tools which is the backbone of this ... See full document
123
Ru-based Gate Electrodes for Advanced Dual-Metal Gate CMOS Devices
... in gate-stack structures consisting of high-K gate dielectrics and metal gate ...transparent gate electrode materials will allow oxygen to penetrate through the gate electrode and ... See full document
257
Interaction of Metal Gatew with High-K Gate Dielectrics in Advanced CMOS Devices
... the gate dielectric. However, the underlying gate dielectric can get damaged by the bombardment of plasma ions which can increase charges and gate leakage ...the gate dielectric and a tight ... See full document
258
Optimization of Metal Gate Electrode Stacks for Work Function Tuning
... metal gate should have an appropriate work function for NMOS or PMOS ...NMOS devices and ~5eV for PMOS ...metal gate electrodes can be used in CMOS processing however with a more complex process ... See full document
180
Fabrication and Device Characterization of Alternative Gate Stacks Using the Non Self-Aligned Gate Process
... p-channel devices, dual metal gate electrodes are needed in order to have appropriate metal work functions for each ...of Si [75]. There have been some efforts to use a single metal gate ... See full document
198
Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors
... alternative gate dielectrics for future generations of ...κ gate stacks using physical and electrical characterization techniques, to gain a better understanding of some important factors associated ... See full document
171
Improved self gain in deep submicrometer strained silicon germanium pMOSFETs with HfSiOx/TiSiN gate stacks
... of gate lengths from 1 µm to 55 nm was etched after which halo and junction implantation is ...[7]. Si control pMOSFETs were co-fabricated under the same processing ...a strained SiGe ... See full document
19
A Study of Group III Elements (La, Gd, Eu, and Al) Incorporation on Metal Gate / High–k Stacks for Advanced CMOS Applications
... poly–silicon gate for NMOS and p+ poly–silicon gate for PMOS which accomplished by ion implantation and subsequent ...sub–micron devices, the energy of implantation and dopant activation temperatures ... See full document
218
Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics
... (CMOS) devices considerable radio frequency (RF) contenders where bipolars and high-electron- mobility-transistors are traditionally dominant [1, ...CMOS devices has further improved the high speed ... See full document
34
The impact of self heating and SiGe strain relaxed buffer thickness on the analog performance of strained Si nMOSFETs
... analog devices where the duty cycle is higher (the MOSFET is on for longer periods of time) and the drain conductance behaviour of the MOSFET is important because of its relationship with the output resistance and ... See full document
35
Performance enhancements in scaled strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks
... from similar structures reported in literature [11, 22]. The TiSiN gates were formed by sputtering. After gate definition, source-drain implants were formed by a 10 keV B implantation with a dose of 1.4x10 15 cm ... See full document
37
Improved analog performance in strained Si MOSFETs using the thickness of the silicon germanium strain relaxed buffer as a design parameter
... length devices, the peak of the electric field does not coincide with the temperature ...These advanced simulation techniques are required for modeling nanoscale hot-electron effects, temperature sensitive ... See full document
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