[PDF] Top 20 WRL 89 1 pdf

... Organizing the modules in this manner simplifies porting the compiler to a new system as no host system with an existing implementation is needed. Instead, all work can be done on the target system: the machine-dependent ... See full document

... The MultiTitan instruction set consists of two instruction formats (see Figure 4). Registers to be fetched in the instruction fetch stage appear in the same place in both formats, so decoding of the format is not ... See full document

... Frequency and voltage scaling, like cache misses, also offer the potential for addi- tional power states that can be cycled through rapidly. The impact that frequency and voltage scaling may have is suggested by the ... See full document

... Many papers on the choice of skip groups have been written, but all of them treat the problem without considering some important details. They restrict it, sometimes implicitly, to a particular implementation and to the ... See full document

... on Architectural Support for Programming Languages and Operating Systems p. 100-104. A more detailed version is available as WRL Research Report 87/1. [22] David W. Wall. Register windows vs. register ... See full document

... We have shown that very long traces give a great deal of information about a program’s be- havior and that using traces that are too short can lead to erroneous performance estimation. We have not yet dealt with the ... See full document

... To get a better understanding of the effects of non-uniform latencies, imagine a machine where the latency for one operation is much larger than the others. In the limit, the performance is not given by the long ... See full document

... A summary of the instruction set is presented in Table 1. The encoding of the instruction fields was chosen to simplify decoding as much as possible. Although the opcode is four bits, many control functions can be ... See full document

... only 1% of the signals are not integrated into the core processor but they are on the critical path of the machine, the system performance will still be ... See full document

... A cache-consistency mechanism roughly intermediate between that of NFS and Sprite has been implemented for the System V Remote File Sharing (RFS) system [1]. As in NFS, clients write-through to the server, so the ... See full document

... Accurate shot size control is a precondition for dot shape control. Given good control of size, the dot shape is determined by the dispense tip shape and size, and by the height from which the dot is released. It is also ... See full document

... Consider a superscalar and superpipelined machine, both of degree three, issuing a basic block of six independent instructions (see Figure 11). The superscalar machine will issue the last in- struction at time t ... See full document

... A second way to implement the reduction is with a vector ALU instruction. (Actually, all of the scalar adds in the previous example were vectors of length 1.) This is illustrated in Figure 6. In this example, we ... See full document

... Initial benchmarks using Synopsys to generate adders and multipliers yielded structures that were larger and slower than we expected. IBM’s parameterized libraries weren’t any better. These results, coupled with our non- ... See full document

... In spite of these drawbacks, network code is still usually put in the kernel because the drawbacks of putting it outside the kernel seem worse. If a single user-level process is used for demul- tiplexing packets, then ... See full document

... We may be able to record them in the call graph as if they were separate calls to every procedure that is assigned to a procedure variable, but we may need to do some dataflow and aliasi[r] ... See full document

... The lifetime of the Itsy greatly varies depending on the workload. In sleep mode, the Itsy can keep the memory re- freshed for almost 13 days. When not in sleep mode, the battery lifetime varies from 40 hours, when idle, ... See full document

... Almes and Lazowska [1] continue the analysis of the experimental Ethernet. They present values of response time as a function of G. They show that for small packet sizes, the response times stays under 1 ... See full document

... order 1 2 3 4 5 6 7 8 1 2 is L L L L L L L S L S , reassembly of L cannot succeed, despite adequate buffer ...space. 1 2 3 4 5 6 7 1 8 2 Upon reception of S , the reassembly process could ... See full document

... Analogous to clamping minorRadius and majorRadius to 1, we also use a single probe in the smallest 1 x 1 mip- map. This reduces cycles spent displaying a repeated tex- ture in the distance. We don’t ... See full document