[PDF] Top 20 WRL 91 2 pdf

... The tracing and simulations were done on a DECstation 5000, using an updated version of the WRL address tracing tools [2]. Application programs are instrumented by inserting code at the start of each basic ... See full document

... Another refinement is that the incremental allocation algorithm has to be concerned with page clusters. Scanning occurs on the granularity of one page cluster at a time, so the length of a garbage collection pause is ... See full document

... Out of the hundreds of papers on caches in the last 15 years [15, 16], Smith [13] was the only paper to exclusively deal with write issues. This paper discussed write buffer performance for write-through caches, but did ... See full document

... section 2, it was noted that while TCP connections are properly identified by the quadruple (src-host, src-port, dst-host, dst-port), the tracing software for these experiments used the triple (src-port, dst-host, ... See full document

... An address trace is the sequence of instruction or data addresses referenced by a program during the course of its execution. Such a trace is useful in simulating the performance of different cache configurations. ... See full document

... An early disclosure of a hardware implementation of the interleaved fin concept had one set of fins as an integral part of the coldplate [7]. The second set consisted of individual fins which floated in the spaces ... See full document

... The thermosiphon device used in this study could operate in a variety of regimes. When there was no heat supplied to the system, and the liquid and vapor were at thermodynamic equilibrium, the pressure in the system ... See full document

... To estimate how merging changes the instruction cache miss rate, the loop average size model described in the previous section can be used. Usually, merging a procedure increases code size. To see how this affects the ... See full document

... T1 was developed at Bell Laboratories in the late 1950s, and the first commercial system was installed in 1962 [20] [21] [22] [23]. Urban cable conduits and manholes were filling up and it was becoming necessary to carry ... See full document

... In theory, this approach seems attractive because it is pattern independent, giving the designer a worst-case approximation. In practice, it does not work particularly well. When I modified Jouppi’s timing analyzer, TV, ... See full document

... Figure 16 shows a starburst pattern of one-pixel wide lines 2 , magnified 2.3 times to show greater detail, and an- tialiased using a regular 4 x 4 subpixel grid like that in the RealityEngine. Although the 16 ... See full document

... 1 2 3 4 5 6 7 8 1 2 is L L L L L L L S L S , reassembly of L cannot succeed, despite adequate buffer ...1 2 3 4 5 6 7 1 8 2 Upon reception of S , the reassembly process could discard L through ... See full document

... List of Figures Figure 6-1: Daily statistics 23-day trace Figure 6-2: Daily statistics 90-day trace Figure 6-3: Daily ratios 23-day trace Figure 6-4: Daily ratios 90-day trace Figure 6-5[r] ... See full document

... The labels on the columns are: inl method inlining, cha using CHA, fld field analysis, objinl object inlining, split method splitting, stk stack allocation, sync synchronization removal,[r] ... See full document

... are 2 distinct regions of energy consumption here - the period when the one of the bitlines is discharging, and the period when the bitlines have reached a stable nal value (after the bitline has completed ... See full document

... Figure 2-9 An x-y-based layout of printed numbers from a color image Figure 2-10 A y-based layout of printed numbers from a color image Figure 2-11 A null-based layout of printed numbers[r] ... See full document

... Figure 3-10 shows the decoding of the syndrome bits for a half-line. Note that the syndrome bits are complemented in the ErrorLog register, and that this table applies to the uncomplemented syndrome. For single-bit ECC ... See full document

... I implemented this global register allocator in a code generator used for Fortran, C, and Modula-2, and , my colleagues have used it to port the Unix operating system to the new machine. To learn how well it works ... See full document

... At this point, the scheduler has filled as many of the memory stalls and coprocessor stalls in the basic block as it can.* It then looks to see if the block ends with a branch whose slot[r] ... See full document

... Coprocessor ALU instructions are transferred from the CPU over the address bus lines at the beginning of the MEM pipestage. The FPU executes coprocessor ALU instructions whose destination is in the range <0..47>. ... See full document