[PDF] Top 20 WRL 91 10 pdf

... We do intermodule register allocation and pipeline instruction scheduling at link time, using information gathered by the compiler back end.. The mechanism for analyzing and modifying th[r] ... See full document

... Given WRL’s positive experience with ezd, it is natural to ask: why haven’t others provided simple access to a structured graphics server? The record suggests that they have, but there were problems. In the early 80’s, ... See full document

... An important advantage of choosing a design point near the optima is that the connector will exhibit minimal sensitivity to changes of the design parameters. For example, beginning with an optimal design and then making ... See full document

... Another area of complexity involving writes is the policy for handling write data on a write miss. Four options exist: either fetch the line before writing (i.e., fetch-on-write), allocate a cache line and write the data ... See full document

... In order to examine boiling at pressures below 10 kPa for a variety of surface sizes, certain experimental designs were considered. Nucleate boiling is very dependent on cavity size, dis- tribution, and wetting ... See full document

... From 10 one sees that the apparent good performance for Q = 500 usec and the MoreQuick algorithm is nearly useless, because almost no packets meet these ... See full document

... Figure 8 shows that as the miss penalty increases, the loop average size model will suggest fewer procedures be merged.. As Figure 9 shows, this results in progressively fewer 10..[r] ... See full document

... T1 was developed at Bell Laboratories in the late 1950s, and the first commercial system was installed in 1962 [20] [21] [22] [23]. Urban cable conduits and manholes were filling up and it was becoming necessary to carry ... See full document

... As a last illustration of shared TLB behavior, Figure 10 shows a plot for the multi-task mix. Several conclusions are immediate. First, as for tree, the mapping size of the TLBs is the dominant factor in ... See full document

... Hardware is required to control the issuing instructions, to track data flow, and to recover from exceptions. A number of techniques have been used to implement this functionality. Scoreboarding, a technique first ... See full document

... The easiest way to implement ImageText is to clear a background rectangle, then use the PolyText code to paint in the foreground pixels. This simple technique works surprisingly well, and the color server paints all ... See full document

... Organizing the modules in this manner simplifies porting the compiler to a new system as no host system with an existing implementation is needed. Instead, all work can be done on the target system: the machine-dependent ... See full document

... Ethernet, a 10 Mbit/sec CSMA/CD network, is one of the most successful LAN technologies. Considerable confusion exists as to the actual capacity of an Ethernet, especially since some theoretical studies have ... See full document

... The source host requests a visa from that ACS, which if necessary obtains visas from ACSs in other organizations, distributes visa information to the appropriate gateways, and returns th[r] ... See full document

... The literature contains a variety of solutions to this problem. Perhaps the simplest is to have a projection at the end of the dispense tip that allows it to press against the workpiece while main- taining the required ... See full document

... Some of this covers the design and use of the Internet Protocol IP family; some covers the implementation and performance of the IP protocols; some covers the problems involved in constr[r] ... See full document

... A Lisp compiler and runtime system which uses such a collector need not have complete control of the processor in order to force a certain discipline on the stack and registers. A Scheme implementation has been done for ... See full document

... at WRL, which implements this algorithm, generates the optimal distribution in less than a second of VAX 785 CPU time, even for configurations with 128 bits and 4 or more carry-skip ... See full document

... Consider a superscalar and superpipelined machine, both of degree three, issuing a basic block of six independent instructions (see Figure 11). The superscalar machine will issue the last in- struction at time t ... See full document

... A table-driven policy daemon This section describes the design and implementation of screend, a table-driven policy daemon to make datagram access control decisions, to be used with the [r] ... See full document