maximum likelihood Viterbi decoder
Design and Implementation of Convolutional Encoder and Viterbi Decoder
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Implementation of Adaptive Viterbi Decoder on FPGA for Wireless Communication
7
A low complexity maximum likelihood decoder for tail biting trellis
11
Implementation of Convolution Encoder and Viterbi Decoder
8
Design and Implementation of High Speed Low Power Viterbi Decoder
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IMPLEMENTATION OF VITERBI ALGORITHM ON DSP
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Adaptive decoding of convolutional codes
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VLSI Architecture of Configurable Low Complexity Hard Decision Viterbi Decoder Prashant Shirke
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Optimum Viterbi Decoder Design and its Implementation on FPGA
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The Design of Viterbi Decoder with Higher Efficiency
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Design Approach of High Speed Parallel Processed Viterbi Decoder with Pipelining Technique
12
A parallel Viterbi decoder for block cyclic and convolution codes
10
Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog
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Performance and Analysis of Viterbi Decoder Using VHDL
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IMPLEMENTATION OF EFFICIENT CONVOLUTIONAL ENCODER AND MODIFIED VITERBI DECODER
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ERROR CORRECTION SYSTEM USING ARTIFICIAL NEURAL NETWORK
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Design of Asynchronous Viterbi Decoder Using Pipeline Architecture
8
Typical Implementation of VITERBI Decoder for efficient error detection and correction
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The Dual of the Maximum Likelihood
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LOW POWER VITERBI DECODER FOR TCM USING T-ALGORITHM
8