system-on-chip architecture
Design of an AC Servo Controller for a Dynamic Simulation Test System for Hydraulic Excavators Based on a System-on-chip Architecture
... test system for a hydraulic excavator, which is a closed loop system whose core is the AC servo ...test system of the hyd- raulic excavator to produce the corresponding ...
12
A Study on Network-On-Chip architecture using Genetic Algorithm
... communication architecture for SoC (system on ...router architecture inorder to determine shortest ...NoC architecture and measures faulty blocks during run time more ...
12
Design of an AMBA AHB Reconfigurable Arbiter for On-chip Bus Architecture
... typical System-on Chip (SOC) design is having many different IP cores, which are linked together with complex on-chip bus communication ...communication architecture is a primary determinant ...
8
Network-on-Chip Architecture Based on Cluster Method
... With more and more transistors embedded on a chip, the SoC of bus structure is poor at scalability, flexibility, reusability, and programmability. As a rzesult the Network-on-Chip (NoC) [10] has been ...
5
Network on Chip Architecture and Routing Techniques: A survey
... High level of integration in systems with different types of applications is done, where each having its own traffic characteristics. Since the early days of VLSI, using buses is becoming less desirable, especially with ...
5
An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links
... proposed system model, and evaluates its performance in ...multichip architecture is a hybrid network with both wired and wireless ...The system is considered to have 64 cores per chip, and ...
52
Performance Analysis of On-Chip Memory Architecture Exploration of Embedded Processor
... memory architecture for an ...The system designer can then evaluate different cost/performance/power profiles for different realizations of the memory ...
13
A System on a Chip Design of the AES Cryptographic System
... sub-pipelined architecture for encryption/decryption of all the standard key sizes (128, 192 and 256 bits) of ...the architecture was designed using Verilog HDL and simulated with ...proposed ...
8
Survey on Arbitration Techniques Used in On Chip Router Architecture
... In a NOC design, we should consider the need for an arbiter to resolve conflicts on shared resources (i.e., bus or equivalent communication channels) among multiple bus masters (e.g., processors). In a bus- based ...
6
Design and Evaluation of Cubic Torus Network on Chip Architecture
... C. Modified versions of Mesh and Torus Topologies The different modifications of mesh topologies that have been suggested in past by different researchers with the efforts to reduce the diameter and average hop count. ...
5
VHDL Design of Efficient Router Architecture for Network-on-Chip
... ABSTRACT: Network-on-Chip (NoC) is a new research in the direction of communication network into System-on- Chip (SoC). Problems of traditional bus-based SoC can be solved and it will give the better ...
6
Prioritized Direction based Switch for Bufferless Network on Chip Architecture
... the system is comprised of multiple processors and functional ...a system with a small number of ...the chip are not straightforwardly serviced by bus based ...
7
Topology Re Configuration for On Chip Networks with Back Tracking
... multi-core system-on-chip or chip ...reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented with backtracking which ...
6
Design and implementation of IP Core Based Architecture of Telecommand System on chip (SoC) on FPGA
... on system on chip and IP core based design ...a chip to implement complex functions in relatively short ...complete system without having to worry about the correctness or performance of the ...
5
Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray
... reconfigurable architecture of a lab-on-chip (LoC) microarray device capable to process data either in genotyping or in gene expression applications in a fraction of the time that is required by the usual ...
11
A FPGA Stereo Matching Algorithm Modeled By DSP Builder
... an architecture that solves the matching problem on 8-bit 512×512 stereo images by using the SAD as similarity ...This system generates 8-bit sub-pixel disparities on 256×360 pixel images at video rate 30 ...
6
Design and Implementation of Real Time Data Acquisition System in All Programmable System on Chip
... Acquisition System is proposed to implement the system in FPGA-based multicore architectures platform with ZynQ processing System, which is based on task-level pipelining (TaLP) in the ...hardware ...
5
On chip communication architecture power estimation in high frequency high power model
... communication system to analyze the chip into logic ...the chip and recommend a number of power decreasing schemes ...electronic system level (ESL) to provide a solution for two recognizable ...
6
ON-CHIP PERMUTATION NETWORK IN MULTIPROCESSOR SYSTEM ON-CHIP FOR ADDRESSING PERMANENT ERRORS
... The use of spare modules to replace erroneous ones, in array structures, is a long-known fault-tolerant approach [27]. Spare cells and wires are used in field-programmable gate arrays to bypass defective components ...
7
Review Paper on Coarse Grain Reconfigurable Architectures for Multimedia Application
... [12] Architecture targeted to stream based ...operation. Architecture have three type interconnection ...of system increase to mapped various application in this architecture in same ...strong ...
6