Viterbi error-correction decoder
Interleaved Convolutional Code and Its Viterbi Decoder Architecture
7
IMPLEMENTATION OF EFFICIENT CONVOLUTIONAL ENCODER AND MODIFIED VITERBI DECODER
13
Implementation of Adaptive Viterbi Decoder on FPGA for Wireless Communication
7
Design Approach of High Speed Parallel Processed Viterbi Decoder with Pipelining Technique
12
Design And Comparison Of Viterbi Decoder On Spartan-3A (XC3S400A-4FTG256C) and Spartan-3E (XC3S500E-4FT256) Using Verilog
6
IMPLEMENTATION OF VITERBI DECODER WITH VARIABLE CODE RATE
11
Implementation of Adaptive Viterbi Decoder
7
Adaptive decoding of convolutional codes
6
Implementation of Convolution Encoder and Viterbi Decoder
8
LOW POWER VITERBI DECODER FOR TCM USING T-ALGORITHM
8
Performance and Analysis of Viterbi Decoder Using VHDL
9
Design and Implementation of Convolution Encoder and Viterbi Decoder
11
Design and Implementation of Convolutional Encoder and Viterbi Decoder
5
Typical Implementation of VITERBI Decoder for efficient error detection and correction
7
Optimum Viterbi Decoder Design and its Implementation on FPGA
6
Performances of the Decoding Algorithms near Shannon Limit
5
An Efficient Low Power Viterbi Decoder Design using T algorithm
6
ERROR CORRECTION SYSTEM USING ARTIFICIAL NEURAL NETWORK
10
Design of Asynchronous Viterbi Decoder Using Pipeline Architecture
8
Power Efficient Survivor Memory Architecture for Viterbi Decoder
7