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[PDF] Top 20 A Novel Design of a Random Generator Circuit in QCA

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A Novel Design of a Random Generator Circuit in QCA

A Novel Design of a Random Generator Circuit in QCA

... 0.006 mm2 As it can be seen, the results in our approach are drastically better than conventional approaches based on CMOS structures. To show the comparison of the results more precise, we compared the bit rates in ... See full document

7

A Novel Design of Half and Full Adder using Basic QCA Gates

A Novel Design of Half and Full Adder using Basic QCA Gates

... In order to realize half adder using QCA,we need three majority gate and an inverter.The two input A and B are fed simultaneously into two majority gates 1 and 2 ,one of which acts as an[r] ... See full document

5

A novel majority gate approach for implementing efficient qca comparator

A novel majority gate approach for implementing efficient qca comparator

... to design a parallel n-bit full ...Alternative QCA implementations of 1-bit full comparators were recently ...other QCA designs, the latter exhibit reduced delays, area occupancy and number of used ... See full document

8

Design and Analysis of a Random Number Generator on FPGA

Design and Analysis of a Random Number Generator on FPGA

... the random numbers that are generated, the basic CA structure is enhanced in two ...the design of linear feedback shift register (LFSRs) and cellular automata (CA), followed by a review of related works ... See full document

10

A Novel Method for UVM & BIST Using Low Power Test Pattern Generator

A Novel Method for UVM & BIST Using Low Power Test Pattern Generator

... external costly Automatic Test Equipment (ATE). In addition, BIST can provide at speed, in system testing of the Circuit-Under Test (CUT). 1.1.Linear Feedback Shift Register(LFSR) Linear Feedback shift registers ... See full document

7

Novel Subtractor Design Based on Quantum-Dot Cellular Automata (QCA) Nanotechnology

Novel Subtractor Design Based on Quantum-Dot Cellular Automata (QCA) Nanotechnology

... technology. QCA is a nanotechnology which can be implemented, in molecular or atomic size and it is smaller than ...CMOS. QCA technology is one approach for implementing logic circuits with specifications ... See full document

6

A Novel Pseudo Random Number Generator Based on Two Plasmonic Maps

A Novel Pseudo Random Number Generator Based on Two Plasmonic Maps

... pseudo random se- quences, private or secret keys or secret ...pseudo random generators is crucial to ensure secure applications in cryptograhy and to avoid all the various and existing ... See full document

10

Design and Implementation of Arithmetic and Logical Block Using QCA Technology

Design and Implementation of Arithmetic and Logical Block Using QCA Technology

... A novel fault-tolerant full-adder for quantum dot cellular automata is ...A novel fault- tolerant full-adder is proposed in this paper: This component is suitable for designing fault-tolerant QCA ... See full document

8

Area and Delay Efficient Digital Comparator

Area and Delay Efficient Digital Comparator

... new design approach oriented to the implementation of binary comparators in ...uses novel implementation strategies, methodologies and new formulations of basic logic equations to make the comparison ... See full document

8

An Improved Novel 64-Bit QCA Adder

An Improved Novel 64-Bit QCA Adder

... The QCA technology is based on the encoding of binary information in the charge configuration within quantum dot ...the QCA cells provides the required computational ...that QCA can achieve high ... See full document

8

Design a Novel Approach to Verification the Faults in Circuit

Design a Novel Approach to Verification the Faults in Circuit

... In Circuit Under Test (CUT) architectures, the Test Pattern Generator (TPG) utilizes Linear Feedback Shift Register (LFSR) generates pseudo random patterns that increases the switching activity of ... See full document

6

DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE

DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE

... The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the correlation between the successive bits. The simulation ... See full document

6

A Concurrent BIST Architecture for Testing Integrated Circuits with Modified SRAM Cells

A Concurrent BIST Architecture for Testing Integrated Circuits with Modified SRAM Cells

... the circuit operates in parallel and to make testing process faster than the scan based testing ...pattern generator circuit which is designed to generate random test patterns to test faults ... See full document

6

Design of a Novel Reversible Arithmetic Circuit using QCA

Design of a Novel Reversible Arithmetic Circuit using QCA

... such circuit which can be used as both adder and subtractor ...a novel reversible RSG Gate is proposed which can perform both the operations ...This novel circuit does not use any control pin ... See full document

7

Optimization of Code Converters Using Ms Gate in Quantum Dot 	Cellular Automata

Optimization of Code Converters Using Ms Gate in Quantum Dot Cellular Automata

... in QCA have been proposed 2 and a performance comparison was presented ...converters design that is optimized by using proposed Novel MS gate in QCA ... See full document

18

Optimization of Code Converters Using Ms Gate in Quantum Dot Cellular Automata

Optimization of Code Converters Using Ms Gate in Quantum Dot Cellular Automata

... low circuit area. This work proposes a novel binary to grey and grey to binary code converters using an optimized MS gate ...proposed design was compared with the previous work and it was analyzed ... See full document

18

Circuit Extraction and Simulation in the presence of Random and Systematic Process Variations

Circuit Extraction and Simulation in the presence of Random and Systematic Process Variations

... the circuit performance parameters as functions of random variables that represent ...the circuit delay can be modeled as a random variable described as a function of those random ... See full document

61

Implementation of Adder by Using Quantum-Dot Cellular Automata Technology

Implementation of Adder by Using Quantum-Dot Cellular Automata Technology

... new QCA adder design is implemented that reduces the number of QCA cells when compared to existing reported ...to design a CLA QCA one-bit adder, with the same reduced hardware as the ... See full document

10

Evolutionary design and optimization of digital Circuits using Imperialist Competitive Algorithm

Evolutionary design and optimization of digital Circuits using Imperialist Competitive Algorithm

... (Multi-Layer Chromosome Evolutionary Algorithm) [9]. All of these methods try to minimize the number of gates in the circuits, but MLCEA-TC (Multi-Layer Chromosome Evolutionary Algorithm – Transistor Count) [10,11] ... See full document

6

CMOS CHARACTERIZATION, MODELING, AND CIRCUIT DESIGN IN THE PRESENCE OF RANDOM LOCAL VARIATION

CMOS CHARACTERIZATION, MODELING, AND CIRCUIT DESIGN IN THE PRESENCE OF RANDOM LOCAL VARIATION

... available. The simulation time is longer than a simple corner methodology, but the benefit from device-to-device correlation and the addition of local variation analysis should outweigh the time hit and add a level of ... See full document

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