addressable memory
Design of high speed low power Content Addressable Memory (CAM) using parity bit and gated power matchline sensing
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Implementation and Design of High Speed FPGA based Content Addressable Memory
8
Investigations on Implementation of Ternary Content Addressable Memory Architecture in SPARTAN 3E FPGA
6
Design of Low Power NAND-NOR Content Addressable Memory (CAM) Using SRAM
6
Algorithm and Architecture for a Low-Power Content Addressable Memory Based on Sparse Compression Technique
7
A Low Power Content Addressable Memory Implemented In Deep Submicron Technology
8
A survey on different techniques and approaches for low power content addressable memory architectures
8
Low power and high performance hybrid content addressable memory (CAM) in SOI technology
6
Performance Evaluation of Ternary Content Addressable Memory and 3T 2R TCAM
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Analysis And Design of Low Power Content Addressable Memory (CAM) Cell
6
POWER REDUCTION IN CONTENT ADDRESSABLE MEMORY
10
Address Mapping In Content Addressable Memory Interface with A Low Power Approach
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Content Addressable Memory Using Automatic Charge Balancing with Self Control Mechanism and Master Slave Match Line Design
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Low Power and Low Area Master Slave Match Line Design for Content Addressable Memory
8
Precharge Free, Low Power Content Addressable Memory V Deepa, K Sravani & Karnarti Bhargavi
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An Efficient Realization Structure and Synthesis of Ternary Content-Addressable Memory (TCAM) Design Based on Reversible Circuits
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A Novel Realization and Synthesis of Ternary Content Addressable Memory (TCAM) Design Using Reversible Circuits Mukka Nikhitha & Purini Suresh Reddy
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Vertically Partitioned SRAM-Based Ternary Content Addressable Memory
5
LOW LEAKAGE POWER BINARY CONTENT ADDRESSABLE MEMORY CELL
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DESIGN OF LOW POWER PRE-COMPUTATION BASED CAM USING XOR AND GATE BLOCK SELECTION SCHEME
12