content-addressable memory cell
LOW LEAKAGE POWER BINARY CONTENT ADDRESSABLE MEMORY CELL
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A Low Power Content Addressable Memory Implemented In Deep Submicron Technology
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Volume 3, Issue 3, March 2014 Page 467
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Investigations on Implementation of Ternary Content Addressable Memory Architecture in SPARTAN 3E FPGA
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Low Power and Low Area Master Slave Match Line Design for Content Addressable Memory
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Content Addressable Memory Using Automatic Charge Balancing with Self Control Mechanism and Master Slave Match Line Design
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An Efficient Design of Content Addressable Memory (BCAM/TCAM) using Push Rule 6T SARAM Cell N Venkatesh & Mr G Sravan Kumar
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Performance Evaluation of Ternary Content Addressable Memory and 3T 2R TCAM
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A survey on different techniques and approaches for low power content addressable memory architectures
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Low Area and Low Power CMOS technology based RAM and Ternary CAM memory design
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RFID Based Book Tracking in Libraries: Using Bicam
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Designing of MCAM Using 22nm Technology
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Algorithm and Architecture for a Low-Power Content Addressable Memory Based on Sparse Compression Technique
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Design of Low Power NAND-NOR Content Addressable Memory (CAM) Using SRAM
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Low power and high performance hybrid content addressable memory (CAM) in SOI technology
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An Efficient Realization Structure and Synthesis of Ternary Content-Addressable Memory (TCAM) Design Based on Reversible Circuits
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Vertically Partitioned SRAM-Based Ternary Content Addressable Memory
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POWER REDUCTION IN CONTENT ADDRESSABLE MEMORY
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Design of high speed low power Content Addressable Memory (CAM) using parity bit and gated power matchline sensing
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Analysis And Design of Low Power Content Addressable Memory (CAM) Cell
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